The present invention relates to electronic circuits, and more particularly, to interfaces on integrated circuit die.
Field programmable gate arrays (FPGAs) are integrated circuits that contain programmable logic circuits. Often, FPGAs also contain one or more analog circuits, such as a phase-locked loop (PLL) or a delay-locked loop (DLL). The performance of PLLs and other analog circuits are particularly sensitive to noise, especially simultaneous switching noise (SSN). It is generally believed that SSN is caused by the delta current noise in the power distribution network and mutual inductive coupling among many switching input/output buffers.
Circuit elements on an integrated circuit die can be referenced to a common ground voltage to prevent glitches on signals that are transmitted between them. The glitches can degrade signal integrity and circuit performance.
However, a common ground may require shorting the substrate in deep N-wells that should be isolated from noise through a common substrate. Key PLL performance parameters, such as the phase noise, may be compromised when the substrate in deep N-well is shorted to a common ground on the die.
Sensitive analog circuits, such as PLLs and DLLs, should have their power supplies, substrates, and N-wells completely separated from noisy circuits in order to maintain maximum performance. However, separate power supply voltages can fluctuate relative to each other, which can cause signals transmitted between circuits in separate power supply domains to change state.
Therefore, it would be desirable to provide techniques for transmitting signals between analog and digital circuits on an integrated circuit die while providing adequate noise isolation.